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HI5702
August 1997
10-Bit, 40 MSPS A/D Converter
Description
The HI5702 is a monolithic, 10-bit, analog-to-digital converter fabricated in a BiCMOS process. It is designed for high speed applications where wide bandwidth and low power consumption are essential. Its 40 MSPS speed is made possible by a fully differential pipeline architecture which also eliminates the need for an external sample and hold circuit. The HI5702 has excellent dynamic performance while consuming <650mW power at 40 MSPS. Data output latches are provided which present valid data to the output bus with a latency of 7 clock cycles. Refer to the HI5703, HI5746, or HI5767 data sheets for lower power consumption.
Features
* Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . 40 MSPS * 8.3 Bits Guaranteed at fIN = 10MHz * Low Power * Wide Full Power Input Bandwidth . . . . . . . . . . 250MHz * Sample and Hold Not Required * Single-Ended or Differential Input * Input Signal Range . . . . . . . . . . . . . . . . . . . . . . . . 1.25V * Single Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . +5V * TTL Compatible Interface
Applications
* Professional Video Digitizing * Medical Imaging * Digital Communication Systems * High Speed Data Acquisition
Ordering Information
PART NUMBER HI5702KCB HI5702JCB HI5702-EV2 SAMPLE RATE 40 MSPS 36 MSPS TEMP. RANGE (oC) 0 to 70 0 to 70 25 PACKAGE PKG. NO.
28 Ld SOIC (W) M28.3 28 Ld SOIC (W) M28.3 Evaluation Board
Pinout
HI5702 (SOIC) TOP VIEW
Typical Application Schematic
HI5702 3.25V 2.0V VREF+ (7) VREF - (8) (LSB) (28) D0 (27) D1 AGND (12) AGND (6) AGND (14) DGND (2) DGND (21) DGND (4) (26) D2 (25) D3 (24) D4 (20) D5 (19) D6 (18) D7 (17) D8 (MSB) (16) D9 VIN + VIN + (9) VCM (11) VIN VIN - (10) (1) DVCC (3) DVCC (23) DVCC 0.1F CLOCK CLK (22) DFS (15) (13) AVCC (5) AVCC 0.1F + 10F D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 10F AND 0.1F CAPS ARE PLACED AS CLOSE TO PART AS POSSIBLE + 10F DGND AGND BNC
DVCC 1 DGND 2 DVCC 3 DGND 4 AVCC 5 AGND 6 VREF + 7 VREF - 8 VIN+ 9 VIN- 10 VCM 11 AGND 12 AVCC 13 AGND 14
28 D0 27 D1 26 D2 25 D3 24 D4 23 DVCC 22 CLK 21 DGND 20 D5 19 D6 18 D7 17 D8 16 D9 15 DFS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999
File Number
3745.4
4-1505
HI5702 Functional Block Diagram
VCM VINVIN+ S/H BIAS CLOCK CLK
STAGE 1
DFS 2-BIT FLASH 2-BIT DAC
+
-
X2
D9 (MSB) D8 D7 D6 STAGE 9 DIGITAL DELAY AND DIGITAL ERROR CORRECTION D5 D4 D3 2-BIT FLASH 2-BIT DAC D2 D1 + D0 (LSB)
-
X2
STAGE 10
1-BIT FLASH
AVCC
AGND
DVCC
DGND
VREF +
VREF -
4-1506
HI5702
Absolute Maximum Ratings
Supply Voltage, AVCC or DVCC to AGND or DGND. . . . . . . . . . +6V DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to DVCC Analog I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AVCC
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range HI5702KCB/JCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 70oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 9. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER ACCURACY Resolution Integral Linearity Error, INL Differential Linearity Error, DNL (Guaranteed No Missing Codes) Offset Error, VOS Full Scale Error, FSE DYNAMIC CHARACTERISTICS Minimum Conversion Rate Maximum Conversion Rate
AVCC = DVCC = +5V; VREF+ = 3.25V; VREF - = 2V; fS = Specified Clock Frequency at 50% Duty Cycle; CL = 20pF; TA = 25oC; Unless Otherwise Specified TEST CONDITIONS MIN TYP MAX UNITS
10 fIN = DC fIN = DC fIN = DC fIN = DC No Missing Codes No Missing Codes HI5702KCB HI5702JCB fIN = 1MHz fIN = 5MHz fIN = 10MHz 40 36 8.3 51 51 54 -
1 0.5 3 2 0.5 9.0 9.0 8.8 57 57 56 56 56 55 -64 -63 -60 -75 -75 -73 -66 -64 -63 66 64 63 -59
2.0 1 -
Bits LSB LSB LSB LSB MSPS MSPS MSPS Bits Bits Bits dB dB dB dB dB dB dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc
Effective Number of Bits, ENOB
Signal to Noise and Distribution Ratio, SINAD RMS Signal = ------------------------------------------------------------RMS Noise + Distortion Signal to Noise Ratio, SNR RMS Signal = -------------------------------RMS Noise Total Harmonic Distortion, THD
fIN = 1MHz fIN = 5MHz fIN = 10MHz fIN = 1MHz fIN = 5MHz fIN = 10MHz fIN = 1MHz fIN = 5MHz fIN = 10MHz
2nd Harmonic Distortion
fIN = 1MHz fIN = 5MHz fIN = 10MHz
3rd Harmonic Distortion
fIN = 1MHz fIN = 5MHz fIN = 10MHz
Spurious Free Dynamic Range, SFDR
fIN = 1MHz fIN = 5MHz fIN = 10MHz
Intermodulation Distortion, IMD
f1 = 1MHz, f2 = 1.02MHz
4-1507
HI5702
Electrical Specifications
PARAMETER Differential Gain Error Differential Phase Error Transient Response Overvoltage Recovery ANALOG INPUT Analog Input Resistance, RIN Analog Input Capacitance, CIN Analog Input Bias Current, IB Full Power Input Bandwidth Analog Input Common Mode Range (VIN+ + VIN-) / 2 REFERENCE INPUT Total Reference Resistance, RL Reference Current Positive Reference Input, VREF+ Negative Reference Input, VREF Reference Common Mode Voltage (VREF+ + VREF -) / 2 COMMOM MODE VOLTAGE Common Mode Voltage Output, VCM Max Output Current DIGITAL INPUTS Input Logic High Voltage, VIH Input Logic Low Voltage, VIL Input Logic High Current, IIH Input Logic Low Current, IIL Input Capacitance, CIN DIGITAL OUTPUTS Output Logic Sink Current, IOL Output Logic Source Current, IOH Output Capacitance, COUT TIMING CHARACTERISTICS Aperture Delay, tAP Aperture Jitter, tAJ Data Output Delay, tOD Data Output Hold, tH Data Latency, tLAT Power-Up Initialization POWER SUPPLY CHARACTERISTICS Supply Current, ICC Power Dissipation Offset Error PSRR, VOS Gain Error PSRR, FSE NOTES: 10. Parameter guaranteed by design or characterization and not production tested. 11. With the clock off. VIN = 0V VIN = 0V AVCC or DVCC = 5V 5% AVCC or DVCC = 5V 5% 120 600 0.2 1 130 650 mA mW LSB LSB For a Valid Sample (Note 2) Data Invalid Time (Note 2) 5 5 6 5 7 20 ns ps ns ns Cycles Cycles VO = 0.4V VO = 2.4V 3.2 -0.2 5 mA mA pF VIN = 5V VIN = 0V 2.0 7 0.8 10.0 10.0 V V A A pF 2.8 1 V mA (Note 2) (Note 2) (Note 2) 200 1.95 2.575 400 3 3.25 2.0 2.625 6 3.3 2.675 mA V V V Differential Mode (Note 2) (Note 3) (Note 3) -50 0.625 1 7 250 0.2V Overdrive AVCC = DVCC = +5V; VREF+ = 3.25V; VREF - = 2V; fS = Specified Clock Frequency at 50% Duty Cycle; CL = 20pF; TA = 25oC; Unless Otherwise Specified (Continued) TEST CONDITIONS fS = 17.72MHz, 6 Step, Mod Ramp fS = 17.72MHz, 6 Step, Mod Ramp MIN TYP 0.5 0.25 1 1 MAX 1 0.5 UNITS % Degree Cycle Cycle M pF A MHz V
+50 4.375
4-1508
HI5702 Timing Waveforms
ANALOG INPUT
CLOCK INPUT
SN - 1
HN - 1
SN
HN
SN + 1
HN + 1 SN + 2
SN + 5 HN + 5 SN + 6
HN + 6 SN + 7
HN + 7 SN + 8
HN + 8
INPUT S/H
1ST STAGE
B1, N - 1
B1, N
B1, N + 1
B1, N + 4
B1, N + 5
B1, N + 6
B1, N + 7
2ND STAGE
B2, N - 2
B2, N - 1
B2, N
B2, N + 4
B2, N + 5
B2, N + 6
10TH STAGE
B10, N - 5
B10, N - 4
B10, N
B10, N + 1
B10, N + 2
B10, N + 3
DATA UTPUT
DN - 7
DN - 6 tLAT
DN - 2
DN - 1
DN
DN + 1
NOTES: 1. SN : N-th sampling period. 2. HN : N-th holding period. 3. BM, N : M-th stage digital output corresponding to N-th sampled input. 4. DN : Final data output corresponding to N-th sampled input. FIGURE 8. HI5702 INTERNAL CIRCUIT TIMING
ANALOG INPUT tAP tAJ CLOCK INPUT 1.5V 1.5V tOD tH DATA OUTPUT 2.0V DATA N - 1 DATA N 0.8V
FIGURE 9. INPUT-TO-OUTPUT TIMING
4-1509
HI5702 Typical Performance Curves
10.0 9.5 EFFECTIVE NUMBER OF BITS 9.0 8.5 fS = 40 MSPS 8.0 7.5 7.0 45 6.5 6.0 1 10 INPUT FREQUENCY (MHz) 100 40 1 10 INPUT FREQUENCY (MHz) 100 fS = 36 MSPS SFDR (dBc) 60 fS = 40 MSPS 55 70
65
fS = 36 MSPS
50
FIGURE 10. ENOB vs INPUT FREQUENCY
FIGURE 11. SFDR vs INPUT FREQUENCY
60 58 56 54 SINAD (dB) 52 50 48 46 44 42 40 1 10 INPUT FREQUENCY (MHz) 100 fS = 40 MSPS fS = 36 MSPS SNR (dB)
60 58 56 54 52 50 48 46 44 42 40 1 10 INPUT FREQUENCY (MHz) 100 fS = 40 MSPS
FIGURE 12. SINAD vs INPUT FREQUENCY
FIGURE 13. SNR vs INPUT FREQUENCY
-40 -43 -46 POWER (mW) fS = 36 MSPS -49 THD (dBc) -52 -55 -58 -61 -64 -67 -70 1 10 INPUT FREQUENCY (MHz) 100 fS = 40 MSPS
600
560
520
480
440
400 5 10 15 20 25 30 35 SAMPLE RATE (MSPS) 40 45
FIGURE 14. THD vs INPUT FREQUENCY
FIGURE 15. POWER DISSIPATION vs SAMPLE RATE
4-1510
HI5702 Typical Performance Curves
10
(Continued)
8
EFFECTIVE NUMBER OF BITS
9.5
7 fS = 36MHz
9
tOD /tH (ns)
6
tOD
8.5 fS = 40MHz 8
5 tH 4
7.5
7 -40
3 -20 0 40 60 20 TEMPERATURE (oC) 80 100 -40 -20 0 20 40 60 TEMPERATURE (oC) 80 100
FIGURE 16. ENOB vs TEMPERATURE
FIGURE 17. tOH /tD vs TEMPERATURE
80 fS = 40 MSPS 75 EFFECTIVE NUMBER OF BITS 70 DICC/AICC (mA) 65 60 55 50 45 40 -40 -20 0 20 40 60 80 100 TEMPERATURE (oC) DICC AICC
9.25 fIN = fS /4
9
8.75
8.5
8.25 10 15 20 25 30 35 40 CLOCK FREQUENCY (MHz)
FIGURE 18. SUPPLY CURRENT vs TEMPERATURE
FIGURE 19. ENOB vs SAMPLE RATE WITH FIXED 12.5ns CLOCK PULSE WIDTH
10 9.75 EFFECTIVE NUMBER OF BITS 9.5 9.25 fIN = 30 MSPS 9 8.75 fIN = 40 MSPS 8.5 8.25 8 44 46 48 50 52 54 56 DUTY CYCLE (%)
FIGURE 20. ENOB vs DUTY CYCLE
4-1511
HI5702
TABLE 1. PIN DESCRIPTIONS PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 NAME DVCC DGND DVCC DGND AVCC AGND VREF+ VREF VIN+ VINVCM AGND AVCC AGND DFS D9 D8 D7 D6 D5 DGND CLK DVCC D4 D3 D2 D1 D0 DESCRIPTION Digital Supply. Digital Ground. Digital Supply. Digital Ground. Analog Supply. Analog Ground. Positive Reference. Negative Reference. Positive Analog Input. Negative Analog Input. DC Output Voltage Source. Analog Ground. Analog Supply. Analog Ground. Data Format Select. Data Bit 9 Output (MSB). Data Bit 8 Output. Data Bit 7 Output. Data Bit 6 Output. Data Bit 5 Output. Digital Ground. Input Clock. Digital Supply. Data Bit 4 Output. Data Bit 3 Output. Data Bit 2 Output. Data Bit 1 Output. Data Bit 0 Output (LSB). FIGURE 21. ANALOG INPUT SAMPLE-AND-HOLD
VIN VIN +
phase, the VIN pins see only the on-resistance of a switch and CS . The small values of these components result in a typical full power bandwidth of 250MHz. 1 1 2 1
CS CS +
CH
1
-+ CH
VOUT + VOUT -
1
1
As illustrated in the Functional Block Diagram and the Timing Diagram in Figure 1, nine identical pipeline subconverter stages, each containing a two-bit flash and a two-bit multiplying digital-to-analog converter, follow the S/H circuit with the tenth stage being a one bit flash converter. Each converter stage in the pipeline will be sampling in one phase and amplifying in the other clock phase. Each individual sub-converter clock signal is offset by 180 degrees from the previous stage clock signal with the result that alternate stages in the pipeline will perform the same operation. The two-bit digital output of each stage is fed to a digital delay line controlled by the internal clock. The purpose of the delay line is to align the digital output data to the corresponding sampled analog input signal. This delayed data is fed to the digital error correction circuit which corrects the error in the output data with the information contained in the redundant bits to form the final 10-bit output for the converter. Because of the pipeline nature of this converter, the data on the bus is output at the 7th cycle of the clock after the analog sample is taken. This delay is specified as the data latency. After the data latency time, the data representing each succeeding sample is output at the following clock pulse. The output data is synchronized to the external clock by a double buffered latching technique. The output of the digital correction circuit is available in two's complement or binary format depending on the condition of the Data Format Select (DFS) input. Analog Input, Differential Connection The analog input to the HI5702 is a differential input that can be configured in various ways depending on the signal source and the required level of performance. A fully differential connection (Figure 15) will give the best performance for the converter.
VIN+ R VIN+ HI5702 VCM R VINVIN-
Detailed Description
Theory of Operation The HI5702 is a 10-bit fully differential sampling pipeline A/D converter with digital error correction. Figure 13 depicts the circuit for the front end differential-in-differential-out sampleand-hold (S/H). The switches are controlled by an internal clock which is a non-overlapping two phase signal, 1 and 2 , derived from the master clock. During the sampling phase, 1 , the input signal is applied to the sampling capacitors, CS . At the same time the holding capacitors, CH , are discharged to analog ground. At the falling edge of 1 the input signal is sampled on the bottom plates of the sampling capacitors. In the next clock phase, 2 , the two bottom plates of the sampling capacitors are connected together and the holding capacitors are switched to the op-amp output nodes. The charge then redistributes between CS and CH completing one sample-and-hold cycle. The output is a fully-differential, sampled-data representation of the analog input. The circuit not only performs the sample-and-hold function but will also convert a single-ended input to a fullydifferential output for the converter core. During the sampling
FIGURE 22. AC COUPLED DIFFERENTIAL INPUT
4-1512
HI5702
Since the HI5702 is powered by a single +5V analog supply, the analog input is limited to be between ground and +5V, which implies the common mode voltage can range of 0.625V to 4.375V. The performance of the ADC does not change significantly with the value of the common mode voltage. A DC voltage source, VCM , about half way between the top and bottom reference voltages, is made available to the user to help simplify circuit design when using a differential input. This low output impedance voltage source is not designed to be a reference but makes an excellent bias source and stays within the common mode range over temperature. It has a temperature coefficient of about 200ppm. Assume the difference between VREF+, typically 3.25V, and VREF-, typically 2V, is 1.25V in Figure 15. Fullscale is achieved when VIN+ and VIN- inputs are 1.25VP-P , with VINbeing 180 degrees out of phase with VIN+. The converter will be at positive fullscale when the VIN+ input is at VCM + 0.625V and VIN- is at VCM - 0.625V (VIN+ - VIN- = 1.25V). Conversely, the ADC will be at negative fullscale when the VIN+ input is equal to VCM - 0.625V and VIN- is at VCM + 0.625V (VIN+ - VIN- = -1.25V). The analog input can be DC coupled as long as the inputs are within the common mode range, Figure 16.
VIN+ R C VIN+ HI5702 VCM R VINVIN-
sinewave riding on a positive voltage equal to VDC , the converter will be at positive fullscale when VIN+ is at VDC + 1.25V and will be at negative fullscale when VIN is equal to VDC - 1.25V. In this case, VDC could range between 1.25V and 3.75V without a significant change in ADC performance. The simplest way to produce VDC is to use the VCM output of the HI5702. The analog input can be DC coupled as long as the input is within the common mode range, Figure 18.
VIN R VDC C
VIN+
HI5702
VIN-
FIGURE 25. DC COUPLED SINGLE ENDED INPUT
The resistor, R, in Figure 18 is not absolutely necessary but will improve performance. Values of 100 or less are typical. A capacitor, C, connected from VIN+ to VIN- will help common mode any noise on the inputs, also improving performance. Values around 20pF are sufficient and can be used on AC coupled inputs as well. A single ended source may give better overall system performance if it is first converted to differential before driving the HI5702. Also refer to the application note AN9413, "Driving the Analog Input of the HI5702". This application note describes several different ways of driving the analog differential inputs. Reference Input, VREF - VREF+ The converter requires two reference voltages connected to the VREF pins. The voltage range of the part with a differential input will be VREF+ - VREF -. The HI5702 is tested with VREFequal to 2V and VREF+ equal to 3.25V for an input range of 1.25V. VREF+ and VREF - can differ from the above voltages as long as the common mode voltage between the reference pins ((VREF+ + VREF -) / 2) does not exceed 2.65V 50mV and the limits on VREF+ and VREF - are not exceeded. In order to minimize overall converter noise it is recommended that adequate high frequency decoupling be provided at the reference input pin. Digital Control and Clock Requirements
FIGURE 23. DC COUPLED DIFFERENTIAL INPUT
The resistors, R, in Figure 16 are not absolutely necessary but will improve performance. Values of 100 or less are typical. A capacitor, C, connected from VIN+ to VIN- will help common mode any noise on the inputs, also improving performance. Values around 20pF are sufficient and can be used on AC coupled inputs as well. Analog Input, Single-Ended Connection The configuration shown in Figure 17 may be used with a single ended AC coupled input.
VIN R VDC HI5702 VIN+
The HI5702 provides a standard high-speed interface to external TTL logic families. In order to ensure rated performance of the HI5702, the duty cycle of the clock should be held at 50%. It must also have low jitter and operate at standard TTL levels. A Data Format Select (DFS) pin is provided which will determine the format of the digital data. When at logic low the data will be output in offset binary format. When at a logic high the data will be output in a two's complement format. Refer to Table 2 for further information.
VIN-
FIGURE 24. AC COUPLED SINGLE ENDED INPUT
Sufficient headroom must be provided such that the input voltage never goes above +5V or below AGND. Again, assume the difference between VREF+, typically 3.25V, and VREF -, typically 2V, is 1.25V. If VIN is a 2.5VP-P
4-1513
HI5702
Performance of the HI5702 will only be guaranteed at conversion rates above 1 MSPS. This ensures proper performance of the internal dynamic circuits. Similarly, when power is first applied to the converter, a maximum of 20 cycles at a sample rate above 1 MSPS will have to be performed before valid data is available. Supply and Ground Considerations The HI5702 has separate analog and digital supply and ground pins to keep digital noise out of the analog signal path. The part should be mounted on a board that provides separate low impedance connections for the analog and digital supplies and grounds. For best performance, the supplies to the HI5702 should be driven by clean, linear regulated supplies. The board should also have good high frequency decoupling capacitors mounted as close as possible to the converter. If the part is powered off a single supply then the analog supply and ground pins should be isolated by ferrite beads from the digital supply and ground pins. Refer to the Application Note "Using Intersil High Speed A/D Converters" (AN9214) for additional considerations when using high speed converters. Increased Accuracy The VOS and FSE errors as reported on the data sheet can be decreased by further calibration of the ADC. It will be assumed that the converter has offset binary coding. See the A/D code table (Table 2) for the ideal code transitions. The first step would be to center the analog input to the desired midscale voltage. This voltage would then be adjusted up or down in the circuitry driving one side of the input to the HI5702 until the 511 to 512 transition occurs on the digital output. Next, set the analog input to the HI5702 to the desired positive fullscale voltage. Adjust one side of the reference circuit up or down until the 1022 to 1023 transition occurs on the digital output of the converter.
Static Performance Definitions
Offset Error (VOS) The midscale code transition should occur at a level 1/4 LSB above half-scale. Offset is defined as the deviation of the actual code transition from this point. Full-Scale Error (FSE) The last code transition should occur for a analog input that is 13/4 LSBs below positive full-scale with the offset error removed. Full-scale error is defined as the deviation of the actual code transition from this point. Differential Linearity Error (DNL) DNL is the worst case deviation of a code width from the ideal value of 1 LSB. Integral Linearity Error (INL) INL is the worst case deviation of a code center from a best fit straight line calculated from the measured data. Power Supply Rejection Ratio (PSRR) Each of the power supplies are moved plus and minus 5% and the shift in the offset and gain error (in LSBs) is noted.
Dynamic Performance Definitions
Fast Fourier Transform (FFT) techniques are used to evaluate the dynamic performance of the HI5702. A low distortion sine wave is applied to the input, it is coherently sampled, and the output is stored in RAM. The data is then transformed into the frequency domain with an FFT and analyzed to evaluate the dynamic performance of the A/D. The sine wave input to the part is -0.5dB down from full-scale for all these tests. SNR and SINAD are quoted in dB. The distortion numbers are quoted in dBc (decibels with respect to carrier) and DO NOT include any correction factors for normalizing to full scale.
TABLE 2. A/D CODE TABLE OFFSET BINARY OUTPUT CODE (DFS LOW) TWO'S COMPLEMENT OUTPUT CODE (DFS HIGH)
CODE DESCRIPTION Full Scale (FS) FS - 13/4 LSB
1/ FS + 1/ LSB 2 4 1/ FS - 3/ LSB 2 4
(NOTE 1) DIFFERENTIAL M LM L INPUT VOLTAGE S S S S VREF + = 3.25V B BB B VREF - = 2.0V (V) D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1.25V 1.2479V 0.3mV 2.1mV -1.2485V -1.25V 1 1 1 0 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 0 0 1 1 0 0 0 0 1 1 1 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 0 0 1 1 0
11/4 LSB Zero NOTE:
1. The voltages listed above represent the ideal transition of each output code shown as a function of the reference voltage.
4-1514
HI5702
Signal-to-Noise Ratio (SNR) SNR is the measured RMS signal to RMS noise at a specified input and sampling frequency. The noise is the RMS sum of all of the spectral components except the fundamental and the first five harmonics. Signal-to-Noise + Distortion Ratio (SINAD) SINAD is the measured RMS signal to RMS sum of all other spectral components below the Nyquist frequency excluding DC. Effective Number of Bits (ENOB) The effective number of bits (ENOB) is calculated from the SINAD data by ENOB = (SINAD - 1.76 + VCORR) / 6.02 where: VCORR = 0.5dB Full Power Input Bandwidth (FPBW) Full power bandwidth is the frequency at which the amplitude of the digitally reconstructed output has decreased 3dB below the amplitude of the input sine wave. The input sine wave has a peak-to-peak amplitude equal to the reference voltage. The bandwidth given is measured at the specified sampling frequency.
Video Definitions
Differential gain and Differential Phase are two commonly found video specifications for characterizing the distortion of a chrominance (3.58MHz) signal as it is offset through the input voltage range of an ADC. Differential Gain (DG) Differential Gain is the peak difference in chrominance amplitude (in percent) at two different DC levels. Differential Phase (DP) Differential Phase is the peak difference in chrominance phase (in degrees) at two different DC levels.
VCORR adjusts the ENOB for the amount the input is below fullscale. Total Harmonic Distortion (THD) THD is the ratio of the RMS sum of the first 5 harmonic components to the RMS value of the fundamental input signal. 2nd and 3rd Harmonic Distortion This is the ratio of the RMS value of the applicable harmonic component to the RMS value of the fundamental input signal. Intermodulation Distortion (IMD) Nonlinearities in the signal path will tend to generate intermodulation products when two tones, f1 and f2 , are present on the inputs. The ratio of the measured signal to the distortion terms is calculated. The terms included in the calculation are (f1 + f2), (f1 - f2), (2f1), (2f2), (2f1 + f2), (2f1 - f2), (f1 + 2f2), (f1 - 2f2). The ADC is tested with each tone 6dB below full scale. Spurious Free Dynamic Range (SFDR) SFDR is the ratio of the fundamental RMS amplitude to the RMS amplitude of the next largest spur or spectral component in the spectrum below fS /2. Transient Response Transient response is measured by providing a full scale transition to the analog input of the ADC and measuring the number of cycles it takes for the output code to settle within 10-bit accuracy. Overvoltage Recovery Overvoltage Recovery is measured by providing a full scale transition to the analog input of the ADC which overdrives the input by 200mV, and measuring the number of cycles it takes for the output code to settle within 10-bit accuracy.
Timing Definitions
Refer to Figure 1 and Figure 2 for these definitions. Aperture Delay (tAD) Aperture delay is the time delay between the external sample command (the falling edge of the clock) and the time at which the signal is actually sampled. This delay is due to internal clock path propagation delays. Aperture Jitter (tAJ) This is the RMS variation in the aperture delay due to variation of internal clock path delays. Data Hold Time (tH) Data hold time is the time to where the previous data (N - 1) is no longer valid. Data Output Delay Time (tOD) Data output delay time is the time to where the new data (N) is valid. Data Latency (tLAT) After the analog sample is taken, the data on the bus is output at 7th cycle of the clock. This is due to the pipeline nature of the converter where the data has to ripple through the stages. This delay is specified as the data latency. After the data latency time, the data representing each succeeding sample is output at the following clock pulse. The digital data lags the analog input by 7 cycles. Power-Up Initialization This time is defined as the maximum number of clock cycles that are required to initialize the converter at power-up. The requirement arises from the need to initialize the dynamic circuits within the converter.
4-1515
HI5702
AMP
A/D
DSP/P
D/A
AMP
HFA1135 HFA1245
HI5702 HI5703 HI5746 HI5767
HSP9501 HSP48410 HSP48908 HSP48212 HSP43891 HSP43168 HSP43216
HI5780 HI1171
HA5020 HA2842 HFA1115
HFA1135: 350MHz Op Amp with Output Limiting HFA1245: Dual 350MHz Op Amp with Disable/Enable HI5702: 10-Bit, 40 MSPS, A/D Converter HI5703: Low Power, 10-Bit, 40 MSPS, A/D Converter HI5746: Low Power, CMOS, 10-Bit, 40 MSPS A/D Converter HI5767: Low Power, CMOS, 10-Bit, 40 MSPS A/D Converter, with Voltage Reference HSP9501: Programmable Data Buffer HSP48410: Histogrammer/Accumulating Buffer, 10-Bit Pixel Resolution HSP48908: 2-D Convolver, 3 x 3 Kernal Convolution, 8-Bit HSP48212: Digital Video Mixer HSP43891: Digital Filter, 30MHz, 9-Bit HSP43168: Dual FIR Filter, 10-Bit, 33MHz/45MHz HSP43216: Digital Half Band Filter HI5780: 10-Bit, 80MHz, Video D/A Converter HI1171: 8-Bit, 40MHz, Video D/A Converter HFA5020: 100MHz Video Op Amp HA2842: High Output Current, Video Op Amp HFA1115: 350MHz Programmable Gain Buffer with Output Limiting CMOS Logic Available in HC, HCT, AC, ACT, and FCT. FIGURE 26. 10-BIT VIDEO IMAGING COMPONENTS
AMP
A/D
DSP/P
D/A
AMP
HFA3600 HFA3102 HFA3101 HFA1100
HI5702 HI5703 HI5746 HI5767
HSP43168 HSP43216 HSP43891 HSP50016 HSP50110 HSP50210
HI5721 HI5780 HI20201 HI20203
HFA1115
HFA3600: Low Noise Amplifier/Mixer HFA3102: Dual Long-Tailed Pair Transistor Array HFA3101: Gilbert Cell Transistor Array HFA1100: 850MHz Op Amp HI5702: 10-Bit, 40 MSPS, A/D Converter HI5703: Low Power, 10-Bit, 40 MSPS, A/D Converter HI5746: Low Power, CMOS, 10-Bit, 40 MSPS A/D Converter HI5767: Low Power, CMOS, 10-Bit, 40 MSPS A/D Converter, with Voltage Reference HSP43168: Dual FIR Filter, 10-Bit, 33MHz/45MHz HSP43216: Digital Half Band Filter HSP43891: Digital Filter, 30MHz, 9-Bit HSP50016: Digital Down Converter HSP50110: Digital Quadrature Tuner HSP50210: Digital Costas Loop HI5721: 10-Bit, 125MHz, Communications D/A Converter HI5780: 10-Bit, 80MHz, D/A Converter HI20201: 10-Bit, 160MHz, High Speed D/A Converter HFA1115: 350MHz Programmable Gain Buffer with Output Limiting CMOS Logic Available in HC, HCT, AC, ACT, and FCT. FIGURE 27. 10-BIT COMMUNICATIONS COMPONENTS
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HI5702 Die Characteristics
DIE DIMENSIONS: 159.4 mils x 175.2 mils x 19 mils 1 mil METALLIZATION: Type: AlSiCu Thickness: 11kA 1kA SUBSTRATE POTENTIAL (Powered Up): GND (0.0V) PASSIVATION: Type: Sandwich Passivation Nitride + Undoped Silicon Glass (USG) Thickness: Nitride 4.2kA, USG 8kA Total 12.2kA 2kA WORST CASE CURRENT DENSITY: 1.6 x 104 A/cm2 TRANSISTOR COUNT: 4514 DIE DIMENSIONS: Silver Filled Epoxy
Metallization Mask Layout
HI5702
DGND DGND DVCC DVCC D3
D0
D1
AVCC
D2
D4
AGND DVCC
CLK
DGND
VREF+
VREFVIN-
D5
VIN+
D6
D9
D8
AGND
AGND
AVCC
VCM
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DFS
D7
HI5702
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
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